DOE-ILP Assisted Conjugate-Gradient Optimization of High-κ/Metal-Gate Nano-CMOS SRAM

Low power consumption and stability in Static Random Access Memories (SRAMs) is essential for embedded multimedia and communication applications. This paper presents a novel design flow for power minimization of nano-CMOS SRAMs, while maintaining their stability. A 32 nm High-κ/Metal-Gate SRAM has been used as example circuit. The baseline SRAM circuit is subjected to power minimization using a dual-Vth assignment based on a novel combined Design of Experiments and Integer Linear Programming (DOE-ILP) approach. However, this leads to a 15% reduction in the Static Noise Margin (SNM) of the SRAM cell, which is an indicator of the stability of the cell. The conjugate gradient optimization overcomes this SNM degradation while reducing the power consumption. The final SRAM design shows 86% reduction in power consumption (including leakage) and 8% increase in the SNM compared to the baseline design. The variability analysis of the optimized cell is performed considering the effect of 12 parameters. SRAM arrays of different sizes are constructed to deminstrate the feasibility of the proposed SRAM cell. To the best of the authors’ knowledge, this is the first study which makes use of Design of Experiments, Integer Linear Programming and conjugate gradient method for simultaneous stability and power optimization in High-κ/Metal-Gate SRAM circuits. Index Terms Highκ/Metal-Gate, Nanoscale CMOS (Nano-CMOS), Static Random Access Memory (SRAM), Power Consumption, Dual-Vth, Leakage Dissipation, Static Noise Margin (SNM)